IEEE/ISO/IEC 14575-2000

$49.00

ISO/IEC 14575:2000 (IEEE Std 1355-1995) Information Technology -- Microprocessor systems -- Heterogeneous InterConnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction)Institute of Electrical and Electronics Engineers/ISO/IEC / 22-May-2001 / 272 pages

The scalable coherent interface (SCI) provides computer-bus-like services but, instead of a bus, uses a collection of fast point-to-point unidirectional links to provide the far higher throughput needed for high-performance multiprocessor systems. SCI supports distributed, shared memory with optional cache coherence for tightly coupled systems, and message-passing for loosely coupled systems. Initial SCI links are defined at 1 Gbyte/s (16-bit parallel) and 1 Gb/s (serial). For applications requiring modular packaging, an interchangeable module is specified along with connector and power. The packets and protocols that implement transactions are defined and their formal specification is provided in the form of computer programs. In addition to the usual read-and-write transactions, SCI supports efficient multiprocessor lock transactions. The distributed cache-coherence protocols are efficient and can recover from an arbitrary number of transmission failures. SCI protocols ensure forward progress despite multiprocessor conflicts (no deadlocks or starvation).

Keywords: low control,encoding schemes,OMI/HIC,packet routing,parallelism,point-to-point serial scalable interconnect,protocols,routing fabric,serial links,serialization,silicon integration,switch chip,transaction layer,wormhole routing
Product Code(s): STD94950




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